SPA 5.0:.sasign : { .U16*, .S16 }{@{!}Pg}XMAD{.sasign.sbsign}{.PSL}{.cop}{.MRG}{.X}Rd{.CC}, Ra{.halfselA}, Sb{.halfselB}, Sc{&req_6}{?sched};
.sbsign : { .U16*, .S16 }
Source formats
.PSL : the product is shifted left 16 bits before being presented to
the adder (used for IMUL.LO emulation)
.cop : { .C32*, .CLO, .CHI, .CBCC, .CSFU }
Controls the selection of the "C" input to the adder
.C32: All 32-bits of the Sc value are presented to the adder
.CLO: Bits [15:0] of the Sc value are presented to the adder
(zero extended)
.CHI: Bits [31:16] of the Sc value are presented to the adder
(Sc >> 16, zero extended).
.CBCC: (Sb[15:0]<<16 + Sc) is presented to the adder (used
for IMUL.LO emulation). .CBCC with Sb(#IMM16) is
discouraged.
.CSFU: Sc + signed-fix-ups is presented to the adder (see
below). Useful for S32 * S32 -> S64 kinds of emulation.
.CSFU with Sb(#IMM16) is discouraged.
.MRG : Merge Sb[15:0] into high 16-bits of the result (used for
IMUL.LO emulation). .MRG with Sb(#IMM16) is discouraged.
.X : use CC.CF and CC.OF as two separate carry inputs to the adder.
.CC : Write CC
.halfselA : { .H0*, .H1 }
.halfselB : { .H0*, .H1 }
XMAD allows the following source combinations for Sb & Sc:
Sb(register) Sc(register)
Sb(#IMM16) Sc(register)
Sb(constant with immediate address) Sc(register)
Sb(register) Sc(constant with immediate address)
Note: Although the following combinations are legal, they are unlikely to
give the desired results because they expect Sb to be a full 32-bit number:
*.CBCC with Sb(#IMM16)
*.CSFU with Sb(#IMM16)
*.MRG with Sb(#IMM16)
Note: The following combinations are illegal:
Sb.{H0,H1} with Sb(#IMM16) -- when using #IMM16 as Sb, there is no need (and no ability) to select something else.
The #IMM16 provides the value for Sb[15:0], and SB.H0 is implicitly selected.
*.CBCC with Sb(constant with immediate address)
*.CBCC with Sc(constant with immediate address)
*.PSL with Sc(constant with immediate address)
*.MRG with Sc(constant with immediate address)
Multiply two 16 bit sources, and add one more.
XMAD executes on both FXU and FMAI, so XMAD has high throughput characteristics.
The basic operation theory of operation is:
Result1 = op1(A * B)
Result2 = Result1 + cop(C)
D = op2(Result2)
// D0 = (A0 * B0)[31:0] + C0
//
XMADD0, A0.H0, B0.H0, C0 ?WAIT1;
XMAD.MRGT1, A0.H0, B0.H1, RZ ?WAIT6;
XMAD.PSL.CBCCD0, A0.H1, T1.H1, D0;
// D1 = (A0 * B0)[63:32] + C1
// A0 is U32, B0 is U32
//
XMADT0, A0.H0, B0.H0, RZ ?WAIT1;
XMADT1, A0.H0, B0.H1, RZ ?WAIT1;
XMADD1, A0.H1, B0.H1, C1 ?WAIT4;
XMAD.CHIT0, A0.H1, B0.H0, T0 ?WAIT6;
IADD3.RSD1, T0, T1, D1;