IADD3

SPA 5.0:
        {@{!}Pg}   IADD3{.X}         Rd{.CC}, {-}Ra, {-}Sb, {-}Rc                                 {&req_6}   {?sched}   ;   
        {@{!}Pg}   IADD3{.dir}{.X}   Rd{.CC}, {-}Ra{.partsel}, {-}Rb{.partsel}, {-}Rc{.partsel}   {&req_6}   {?sched}   ;   

  .dir     : { .NS*, .LS, .RS }
             .NS : after adding A and B, the sum is added to C
             .RS : after adding A and B, the sum is shifted right by 16 before being added to C
             .LS : after adding A and B, the sum is shifted left by 16 before being added to C
  .X       : when specified, both CF.OF & CF.CC are two separate carry inputs to the adder.
  .CC:     : Write condition codes
  .partsel : { .32*, .H0, .H1 }

IADD3 allows the following combinations:
    Sb(register)
    Sb(#IMM20) (sign extended)
    Sb(constant with immediate address)

IADD3 only supports {.dir} and {.partsel} specifiers when Sb is a register (i.e. "Rb", not "Sb").
When {.dir} and {.partsel} are not (or cannot) be specified, the semantics are those
of .NS and .32, respectively.

IADD3 only supports the following combinations of source negates:
     Ra +  Sb +  Rc
     Ra +  Sb + -Rc
     Ra + -Sb +  Rc
     Ra + -Sb + -Rc
    -Ra +  Sb +  Rc
    -Ra +  Sb + -Rc
In short, all combinations are allowed except those negating both -Ra and -Sb at the same time.
Note that (-Ra + -Sb + Rc) can be achieved by swapping the Ra and Rc arguments, which are fully
symmetric for IADD3.NS, thus allowing all combinations of negates except the negation of all
three inputs for normal 3-input adds.

Add three sources ((A + B) + C), possibly shifting the result of A +B by 16 bits (either left or right) before adding C. Optionally produces (with .CC) and consumes (with .X) two carry bits, in CC.OF and CC.CF, compatible with the format of CC used by XMAD. Allows for optional negation of up to 2 of its three arguments. In the three register form, each input can be the 32-bit register, or the high or low (unsigned) 16-bit half of the register. So, for example, a three input (unsigned) 16-bit add is possible, producing an 18-bit result in Rd (i.e. IADD3 Rd, Ra.H0, Rb.H0, Rc.H0).

An extended-precision add is performed by processing words in order from least-significant to most-significant, adding with carry-in for all but the initial IADD3. The zero flag (CC.ZF) is accumulated when .X is used, so it provides an overall zero-detect.

IADD3 : 3-input Integer Addition

Format:

Description:

Examples: