S2R : Move Special Register to Register

warp input primitive type and size
Return values are:                        


    
 Shader 
    
 SR read value 


    
 VSa:     
    
 POINT,LINE,TRIANGLE,PATCH 


    
 VSb:     
    
 POINT,LINE,TRIANGLE,PATCH 


    
 TI/TS:   
    
 POINT,LINE,TRIANGLE,PATCH 


    
 GS:      
    
 POINT,LINE,TRIANGLE,PATCH 


    
 PS:      
    
 0                         


    
 Compute: 
    
 0                         


Where


    
 Type 
    
 Enum value 


    
 POINT    
    
 0x0001                              


    
 LINE     
    
 0x0002 | (adjancency << 8)    


    
 TRIANGLE 
    
 0x0004 | (adjancency << 8)    


    
 PATCH    
    
 0x0008 | (size of patch << 8) 

Primitive invocation id (when hw generates multiple instances of a primitive)                 
GS Shaders:                                                                           
  Hw is  generating multiple instances: return(invocation id) in range of [0,InvocationCount-1] 
  Hw not generating multiple instances: return(0)                                               
TI/TS Shaders:
  return(invocation id); [0,InvocationCount-1]                                                  
Other Shaders:
  return(0) 

A floating point number (either -1.0 or +1.0) tied to the SetWindowOrigin method.         
It can be combined with an FMUL to correct the sign of the y derivitives calculated       
in an OpenGL program to insure they work for both render-to-texture and normal rendering. 


    
 SetWindowOrigin.Mode 
    
 SR read value 


    
 UPPER_LEFT 
    
 +1.0f 


    
 LOWER_LEFT 
    
 -1.0f 

A boolean register value indicating if the thread has been killed.                                  
Helper pixels (pixels with no coverage used to round out quads) start execution in a killed state.   
Pixel shaders can also use be killed with the KIL instruction.             
A pixel thread that is killed  will have it's outputs automatically discarded and                    
is not allowed to execute global store commands.                                                     
PS Shaders:
if(thread has been killed or is helper pixel): 
      return(0xffff_ffff)                               
else:
      return(0)                                                                                 
Other Shaders:
      return(0)                                                                                         

Read the shader type of the currently running thread (Enumerated as below)


    
 ShaderType 
    
 Value 


    
 Vertex A           
    
 0 


    
 Vertex B           
    
 1 


    
 Tessellation Init  
    
 2 


    
 Tessellation       
    
 3 


    
 Geometry           
    
 4 


    
 Pixel              
    
 5 


    
 Compute            
    
 6 

A completely SW defined value, set with a PRI.  
Possible uses might include
    - Affinity interpretation: enum value telling how to interpret affinity
    - Double Precision or not bit
    - Family & Chip Codes
    - ISA codes

Presented to all warps that enter the trap handler.
Results undefined if PRI is changed when SM is not paused.

Indicates that the SM is in single step mode.  In the absence of other bits set in the 
Error Status Register, this is the primary indication of why a warp enters a trap handler.
This is controlled by the PRI_SM_DBGR_CONTROL0.SINGLE_STEP_MODE (settings are ENABLE/DISABLE).

Enumeration Values:
  0: NORMAL - no preemption request in progress
  1: PREEMPTION_SAVE - preemption save in progress
  2: PREEMPTION_RESTORE - preemtion restore in progress

Contains state that must be visible to all warps or errors that cannot be charged to a single warp.
Presented to all warps that enter the trap handler.
Results undefined if PRI is changed when SM is not paused.
Semantics:
  - Global errors caused by warps outside of the trap handler are not guaranteed by HW to be 
    reported before entering trap handler.  SW must flush global faults (e.g., L1 store faults) 
    by using a CCTL.IVALL operation.
  - Global errors are not disabled while in the trap handler.  (There is no double buffering.)
  - Global errors caused by warps inside the trap handler are not guaranteed by HW to be reported before 
    leaving the trap handler.  SW must flush and check for global faults before RTT.
  - Cleared by CPU while SM is paused via PRI.

Indicates CPU has instructed this SM to stop.  All warps should prepare
state and then execute a BPT.PAUSE to yield control to the CPU.
This is controlled by the CPU writing to PRI_SM_DBGR_CONTROL0.STOP_TRIGGER.
Note that if any warp is executing IDE critical section (i.e instructions between IDE.DI and  IDE.EN), 
then CPU_STOP is delayed, until no warp is in critical section. However if PRI_SM_DBGR_CONTROL0.STOP_IS_NOT_MASKABLE is set, 
then check for any warp being in critical section is not performed while processing CPU_STOP event.
Setting PRI_SM_DBGR_CONTROL0.STOP_IS_NOT_MASKABLE is expected to be used by the CPU to debug code in IDE critical section.

Indication if any warp is in IDE critical section. 

Multiple Warp Errors
Indicates that a warp error occurred while this SM's warp error register was non-zero (a warp error is still
pending) on this SM.  Since the second error's information (including its warp number) cannot be captured,
the multiple errors bit is indication that at least one error has been lost.

Single Warp Error
Indicates that a warp error has been detected on this SM and that error has not yet been cleared (by 
the CPU via PRI).  When warp errors are cleared via PRI, this state is cleared immediately.  

Warp Trap 1 
Indicates that at least one warp on the SM executed BPT.TRAP with an immediate of 1.

Warp Trap 2+
Indicates that at least one warp on the SM executed BPT.TRAP with an immediate of 2 or greater. 

   Contains errors known to be caused by this thread's warp.
   These error are presented only to the warp that is responsible for the error.
   Semantics:
     - Only the first-detected warp error from a single warp is reported.  
     - If more than 1 warp error is seen, then "Multiple Warp Errors" is set and subsequent errors from the 
       same warp or from other warps are lost. (There is no double buffering)
     - All warp errors will be reported before entering the trap handler.
     - All warp errors caused be any warp in the trap handler will be ignored.  Innocuous ones will be allowed silently 
       and blatantly dangerous/corrupting ones will result in immediate and silent warp termination.
     - Error status is not cleared after the warp that caused the error reads SR_WarpErrorStatus.
   Enumeration Values:
     0: no errors
     1: STACK_ERROR
     2: API_STACK_ERROR
     3: Not Used 
     4: PC_WRAP
     5: MISALIGNED_PC
     6: PC_OVERFLOW
     7: Not Used
     8: MISALIGNED_REG
     9: ILLEGAL_INSTR_ENCODING
    10: Not Used
    11: ILLEGAL_INSTR_PARAM
    12: INVALID_CONST_ADDR
    13: OOR_REG
    14: OOR_ADDR
    15: MISALIGNED_ADDR
    16: INVALID_ADDR_SPACE
    17: Not Used 
    18: INVALID_CONST_ADDR_LDC
    19: Not Used
    20: Not Used 
    21: Not Used 
    22: PHYSICAL_STACK_OVERFLOW
    23: MMU_FAULT
 

Non-zero indicates that this warp personally executed a BPT.TRAP
instruction.  The BPT.TRAP immediate is provided in this field.
BPT.TRAP 0; is illegal.
Cleared on RTT