IDE.action : Interrupt disable/enable

This instruction enables/disables specific interrupt sources corresponding as indicated by the immediate value. The immediate value represents a bitfield that corresponds to interrupt status bits in SR_GlobalErrorStatus.

Software Note

The motivation for providing this instruction was to provide a way to implement a critical section for a warp. This is a warp wide instruction, in that the first thread to execute this instruction does so for the entire warp. In SPA 3.5 only one value of immediate is supported which corresponds to enabling /disabling of interrupts BPT.TRAP (1..6) and CPU_STOP interrupt. Note, BPT.TRAP 7 and warp errors cannot be disabled. When a warp is launched, it starts with all interrupts enabled.

WARNING Avoid using any synchronization instructions such as BAR within the critical section. Note that the ISA specification does not require the implementation to report any errors in such cases nor does it require the BAR instructions be converted to NOP instruction. The HW will disallow any further IDE.DIS instructions from being executed once the warp's coalescing window for BPT.TRAP is complete in order to bound trap latency. Similarly use of OFF_DECK_PIXBAR opex hint is not allowed in critical section since it requires other warps in subtile to be launched, which may not be possible.

Examples:

#example sequence using IDE to safely read SM's virtual ID and use that do some address calculation
IDE.DI      0xC10;    // corresponds to global ESR register bits 10-11 (BPT.TRAP) and bit 4 (CPU_STOP) interrupts
S2R	R5,  SR_VirtId ;
//Do some address computation
IDE.EN     0xC10;     // corresponds to global ESR register bits 10-11 (BPT.TRAP) and bit 4 (CPU_STOP) interrupts