SPA 5.0:{@{!}Pg}VSHR{.dfmt}{.safmt.sbfmt}{.mode}{.SAT}{.op2}Rd{.CC}, Ra{.partselA}, Rb{.partselB}, Rc{&req_6}{?sched};.dfmt: { .UD, .SD* } Destination format (unsigned or signed) .safmt: { .U32, .S32*, .U16, .S16, .U8, .S8 } .sbfmt: { .U32*, .U16, .U8 } .ifmt: { .U16* } Source formats .mode: { .C*, .W} .C (Clamp): Rb/#imm16 is treated as an unsigned integer and is clamped to (0-32). // Default mode. .W (Wrap): Rb/#imm16 is treated as an unsigned integer and is masked by 0x001f .op2: { .PASS*, .MRG_16H, .MRG_16L, .MRG_8B0, .MRG_8B2, .ACC, .MIN, .MAX} .CC: Write condition codes .partselA: if (.U8|.S8) { .B0*, .B1, .B2, .B3 } if (.U16|.S16) { .H0*, .H1 } .partselB: if (.U8) { .B0*, .B1, .B2, .B3 } if (.U16) { .H0*, .H1 }{@{!}Pg}VSHR{.dfmt}{.safmt.ifmt}{.mode}{.SAT}{.op2}Rd{.CC}, Ra{.partselA}, #imm16, Rc{&req_6}{?sched};
Shift Ra right by contents of Rb/#imm16 with optional second stage operation and optional saturate.
Ra >> Rb or #imm16, promoted to an S34 value to match the data pipe of the other scalar video instructions. The msb insertion is sign_bit for {S32|S16|S8} and 0 for {U32|U16|U8}.
VSHR.W R0, R1, R7, RZ; VSHR.UD.U32.U16 R0, R1, 0x9, RZ;