VMAD : Integer Byte/Short Multiply Add

Multiply and add sources into destination.

The set of datapaths VMAD can be dispatched to depend on widths of Ra/Rb operands.

Basic math operation:

Depending on the sign of the Ra and Rb/#imm16 operand, and the negates for Ra/Rb/Rc/#imm16, the following combinations of operands are supported for VMAD:

(Here the input operands Ra/Rb/#imm16 are extended to full 32 bits, even if they were specified as U16/S16 or U8/S8.)

    tmp =  (Ra  * Rb ) + Rc:
    tmp =  (Ra  *#imm) + Rc:

    tmp =  (U32 * U32) + U32   // intermediate unsigned; final unsigned
    tmp = -(U32 * U32) + S32   // intermediate   signed; final   signed
    tmp =  (U32 * U32) - U32   // intermediate unsigned; final   signed
    tmp =  (U32 * S32) + S32   // intermediate   signed; final   signed
    tmp = -(U32 * S32) + S32   // intermediate   signed; final   signed
    tmp =  (U32 * S32) - S32   // intermediate   signed; final   signed
    tmp =  (S32 * U32) + S32   // intermediate   signed; final   signed
    tmp = -(S32 * U32) + S32   // intermediate   signed; final   signed
    tmp =  (S32 * U32) - S32   // intermediate   signed; final   signed
    tmp =  (S32 * S32) + S32   // intermediate   signed; final   signed
    tmp = -(S32 * S32) + S32   // intermediate   signed; final   signed
    tmp =  (S32 * S32) - S32   // intermediate   signed; final   signed

Note: Sass allows optional negates on both Ra and Rb/#imm16 source operands, however this is implemented by negating the result of the product (only if one but not both sources are negated. Since Ra and Rb/#imm16 are not actually negated, VMAD will not detect an overflow in the case where negating the source operand would have caused overflow.

The negate on Ra,Rb/#imm16,Rc and the .PO option is encoded in the 2 bit psign field as follows:

 (A*B)+C 

 (A*B) +  C + 0 

 (A*B)-C 

 (A*B) + ~C + 1 

-(A*B)+C 

~(A*B) +  C + 1 

   .PO   

 (A*B) +  C + 1 

Note: A negate of both Ra and Rb/#imm16 will have no effect.
Note: It is illegal to negate both Rc and the result of the product.
Note: It is illegal to negate any source operand in .PO mode.

The tmp variable will contain enough bits to represent all possible values after the multiply/accumulation. No overflow of the tmp variable will occur.

Sign:

The intermediate sign of the product A*B will be unsigned if:

• Both Ra and Rb/#imm16 are unsigned
• and neither Ra nor Rb/#imm16 are negated.

Else the intermediate sign will be signed.

The sign of Rc is the same as the intermediate sign of the multiply.
If Rc is signed it needs to be properly sign extended to 64 bits before addition/subtraction to/from the product.

The final sign will be unsigned if:

• The intermediate sign is unsigned
• and Rc is not negated ( +Rc ),

Else the final sign will be signed.

Optional Shift Right:

There is a normalization shift after the multiply/accumulate stage:

  2'b00 = .PASS  :  shr = tmp
  2'b01 = .SHR_7 :  shr = tmp >> 7  // sign extended if final result is signed,
                                       zero-extended otherwise
  2'b10 = .SHR_15:  shr = tmp >> 15 // sign extended if final result is signed,
                                       zero-extended otherwise
  2'b11 = illegal

The shr variable will contain enough bits to represent all possible values after the normalization shift. No overflow of the shr variable will occur.

Saturation:

There is an optional saturate of the shifted output:

• If the final sign is unsigned the clamping range will be U32,
• else the clamping range will be S32.

The input to the saturation is the result from the normalization shift:

  result[31:0] = .SAT ? CLAMP(shr, RANGE_MAX, RANGE_MIN) : shr[31:0]

Second stage operation:

There is no second stage operation (unlike the other V* instructions that do byte/short extraction.