VADD : Integer Byte/Short Addition

Format

SPA 5.0:
        {@{!}Pg}   VADD{.dfmt}{.safmt.sbfmt}{.PO}{.SAT}{.op2}   Rd{.CC},{-}Ra{.partselA},{-}Rb{.partselB},Rc   {&req_6}   {?sched}   ;   
        {@{!}Pg}   VADD{.dfmt}{.safmt.ifmt}{.PO}{.SAT}{.op2}    Rd{.CC},{-}Ra{.partselA},{-}#imm16,       Rc   {&req_6}   {?sched}   ;   

 .dfmt:       { .UD, .SD* }
              Destination format (unsigned or signed)

 .safmt:      { .U32, .S32*, .U16, .S16, .U8, .S8}
 .sbfmt:      { .U32, .S32*, .U16, .S16, .U8, .S8}
 .ifmt:       {              .U16, .S16*         }
              Source formats

 .PO:         Plus one (used in computing averages)

 .SAT:        Saturate destination based on .op2 and final sign

 .op2:        { .PASS*, .MRG_16H, .MRG_16L, .MRG_8B0, .MRG_8B2, .ACC, .MIN, .MAX}


 .CC:         Write condition codes

 .partselA:   if (.U8|.S8)   { .B0*, .B1, .B2, .B3} 
              if (.U16|.S16) { .H0*, .H1}

 .partselB:   if (.U8|.S8)   { .B0*, .B1, .B2, .B3} 
              if (.U16|.S16) { .H0*, .H1}

Description

Add sources into destination with optional second stage operation and optional saturate.

Basic math operation:

2's complement addition/subtraction via optional "-" on sources.

Both inputs are are first promoted to S33 (based on their individual .S or .U format), then the optional negate is applied on the applicable inputs. After that the add is done, producing an S34 result.

The negate on Ra, and Rb/#imm16 is encoded in 2 bit .mode field as follows:

mode Operation Mapping Comments
0 
  Ra+Rb 
  A +  B + 0
Add
1 
  Ra-Rb 
  A + ~B + 1
Ra - Rb
2 
 -Ra+Rb 
 ~A +  B + 1
Rb - Ra
3 
 .PO    
  A +  B + 1
Add plus one

It is illegal to negate both sources at the same time.

Note that when .ifmt == S16 is used, the 16-bit immediate is first sign extended, and then the optional negate is applied. This results in non-obvious expansion. E.g.: 

        VADD.U32.S16 R0, R1, -0xffff, R2;  # Computes R0 = R1 -  (-1)  + R2
                                           # but NOT  R0 = R1 - 0xffff + R2

Examples:

VADD                   R0, R1,    R2,    RZ;
VADD.ACC               R0, R1,    R2,    R3;
VADD.UD.U8.U8          R0, R1.B3, R2.B1, RZ;
VADD.S16.S16           R0, R1.H0, R2.H1, RZ;
VADD.U8.S32            R0, R1.B2, R2,    RZ;
VADD.S16.S8            R0, R1.H0, R2.B1, RZ;
VADD.SD.S16.S32        R0, R1.H0, R2,    RZ;
VADD.SD.SAT.MRG_16H    R0, R1,    R2,    R3;

VADD.U32.S16 R0, R1, -0xffff, R2;  # Computes R0 = R1 -  (-1)  + R2
VADD.U32.S16 R0, R1,  0xffff, R2;  # Computes R0 = R1 +  (-1)  + R2
VADD.U32.U16 R0, R1, -0xffff, R2;  # Computes R0 = R1 - 0xffff + R2
VADD.U32.U16 R0, R1,  0xffff, R2;  # Computes R0 = R1 + 0xffff + R2

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