VABSDIFF4 : Integer SIMD Byte Absolute Difference

4-way SIMD parallel absolute difference with subsequent reduction operation.

Sources (Ra, Rc) and destination (Rd) are all 32b data registers.

The following source Sb is allowed:

    Sb(register)
    Sb(#IMM08)

Basic math operation:

4-way SIMD parallel operation |A - B| done first.

Both inputs are are first promoted to S09 (based on their individual .S8 or .U8 format). After that the absolute difference is done, producing a SIMD U09 result. These are promoted to SIMD S10 values to match the data pipe of the other quad SIMD instructions.

Notes:

• When the reduction operation produces a SIMD result (.red == .SIMD_MRG/.SIMD_MIN/.SIMD_MAX), the reduction step uses the 8 LSBs of each SIMD intermediate result. For these reduction operations, the .SAT specifier as well as the IntermediateSign is honored. IntermediateSign is used to interpret the individual 8 bit values for the SIMD_MIN and SIMD_MAX operations.
• When the reduction operation produces a scalar result (.red == .ACC/.MIN/.MAX), saturation cannot be performed. For these reduction operations, always the un-saturated S10 intermediate result is used in reduction step (the intermediate result is always S10, IntermediateSign is not used to interpret its value). If .SAT is specified, it is an illegal instruction encoding error.

Other operations:

• Optional condition code write.
• Optional sync.

CC Update:

Optional set of Condition Code, based on final 32 bit result in Rd. The setting of CF & OF is based on final reduction operation adder, they are only valid if the reduction operation is .ACC.

ZF = (result==0) ?  1 : 0)
SF = result[31]
CF = if (.red==.ACC) Carry is defined as the carry-out of the msb adder.
     if (.red!=.ACC) 0
OF = if (.red==.ACC) Overflow is defined as the XOR of the resulting sign bit and the real sign bit.
     if (.red!=.ACC) 0

Examples:

VABSDIFF4.S8.U8.ACC R0, R1, R2, R3;
VABSDIFF4.UD.U8.U8.ACC R0, R1, R2, R3;