TLD : Texture Load

SPA 5.0:
        {@{!}Pg}   TLD{.B}.lod{.AOFFI}{.MS}{.CL}{.NODEP}{.phase}   {Ps, } Rd, Ra{, Rb}, #tsPtrIdxU13, #paramA{, #wmskU04}   {&req_6}   {&rdN}   {&wrN}   {?sched}   ;   

  .B:      Bindless mode, where the texture header pointer and sampler pointer is packed into a 32 bit register as:
           samplerPtr[31:20] | headerPtr[19:0]// sampler is not used in this instruction
           Data is sent via register Rb.

  .lod:    LOD adjust mode.
              .LZ - LOD level 0 (finest)       // no register required
              .LL - LOD absolute               // 1 U32 register required\
	       LOD Level 0 actually selects the level set by textureHeader.resViewMinMapLevel.

  .AOFFI:   Programmable Texture Offset.
              _aoffimmi(u,v,w)  [DX10]   // 1 register required
		  ((w & 0xf)<<8) | ((v & 0xf)<<4) | (u & 0xf)
              Each 4b field is a 2's complement integer from -8 to +7.

  .MS:     Programmable Multisample location. 
           .MS can only be used with the .LZ LOD option, and 2D/ARRAY_2D textures.
           .MS cannot be combined with .CL
	      Multisample location             // 1 U32 register required

  .CL:     Enable edge clamp (feature added for video). Normally, per dx10, TLD 
           will return black border color for an out-of-range coordinate or 
           out-of-range array index. When TLD.CL is specified, edge clamping is 
           forced ON. Note that in neither case is the sampler clamping state 
           observed. Note that for 1D-array and 2D-array cases, the array index 
           will also be clamped to [0..array_size-1] when .CL is requested 
	   .CL cannot be combined with .MS

  .NODEP:  Indicates that there is no subsequent quad derivatives to be calculated.
	   Threads that have been "killed" will be disabled to stop unnecessary texture fetches.

  .phase:  Allows control on the current warps texture hash, used for scheduling.
               < NONE >
               .T - postfix increment of the 3 bit texture component of the hash.
	       .P - postfix increment of the 5 bit phase component, and zero out the 3 bit texture component of the hash. 

Ps:
            Predicate returning sparse tile status. Indicate that the surface access is happening to a page marked as sparse (valid, not mapped).


Immediate Inputs:

  #tsPtrIdxU13:
	 This immediate index (word address) is used to fetch the packed header+sampler pointer entry from constant cache.  The bank from
	 which it is fetched is determined by bundle state. The constant bank entry is 32 bit structure of the form
	 "samplerPtr[31:20] | headerPtr[19:0]". Only headerPtr is used by this instruction.
	 Note: Ignored if .B option is used.
	 Any header pointer greater than one specified in SetTexHeaderPoolC.MaximumIndex will be regarded as an "invalid"
	 texture (i.e. equivalent to BIND_GROUP_TEXTURE_HEADER_VALID_FALSE in fermi).

#paramA: source coordinate description.

           s,t,r are S32, 
           a is U16 integer

     If the source coordinate description does not match the texture type of the texture header,
     zeroes will be returned.  The array specifiers can be freely used with non-array textures
     (and the opposite holds as well), provided the number of coordinates (1D,2D,3D) matches.

  #wmskU04       destination write mask (decimated contiguous writes)
     Allows for write masking the returning data writes via a bit enable
     for each of R,G,B,A. A four-vector is always returned from TEX.
     #wmskU04 defaults to 0xf.