SUST

SPA 5.0:
        {@{!}Pg}   SUST.D{.BA}.dim{.cop}{.sz}{.clamp}   [Ra], Rb, #tsPtrIdxU13   {&req_6}   {&rdN}   {?sched}   ;   
        {@{!}Pg}   SUST.D{.BA}.dim{.cop}{.sz}{.clamp}   [Ra], Rb, Rc             {&req_6}   {&rdN}   {?sched}   ;   
        {@{!}Pg}   SUST.P.dim{.cop}{.rgba}{.clamp}      [Ra], Rb, #tsPtrIdxU13   {&req_6}   {&rdN}   {?sched}   ;   
        {@{!}Pg}   SUST.P.dim{.cop}{.rgba}{.clamp}      [Ra], Rb, Rc             {&req_6}   {&rdN}   {?sched}   ;   


        .dim    {.1D, .1D_BUFFER, .1D_ARRAY, .2D, .2D_ARRAY, .3D}

        .mode   {.D, .P}
            .D      This mode specifies that surface data is treated as raw data of size .sz, without any format conversion.
                    In this mode, if .BA (ByteAddress) is specified, 
                         the x-coordinate is assumed to be in bytes, aligned on a .sz boundary.
                         Otherwise, x-coordinate is treated as sample coordinate and scaled by .sz in hardware.
            .P      This mode specifies a formatted pixel load from surface. 
                    The x value is a sample coordinate in the target surface.
                    In this mode .rgba specifies the number of components written by the load. 

        .cop    {.WB*, .CG, .CS, .WT}
        .sz     {.U8, .S8, .U16, .S16, .32*, .64, .128}  // used in .D mode, specifes load size of raw data.
        .rgba   {.R, .RG, .RGBA*}                      // used in .P mode, specifies a scalar, vec2 or vec4 destination register.
        .BA     x-coordinate is specified as byte-address. (in .D mode)
        .clamp  {.IGN, .NEAR*, .TRAP}


    Operands
    ------------------------------------
    Ra             Coordinates 
    Rb             Store data 
    #tsPtrIdxU13   This immediate index (word address) is used to fetch the packed header+sampler pointer entry from constant cache.  The bank from which
                   it is fetched  is determined by bundle state. The constant bank entry is 32 bit structure of the form
                   "samplerPtr[31:20] | headerPtr[19:0]". (Surface instructions ignore sample pointers).
                   Any header pointer greater than one specified in SetTexHeaderPoolC.MaximumIndex  will be regarded as an "invalid" texture.
    Rc             In bindless mode, Rc register is used to pass the "samplerPtr[31:20] | headerPtr[19:0]". 
                   Note: Ra/Rc cannot be RZ register.

SUST stores data to pitch or blocklinear surfaces.

Register Ra specifies surface coordinates. The number of coordinates depends upon surface dimension. Ra must follow register alignment rules for given number of coordinates.

*Surface Coordinate packing in Ra*
.dim	Ra	Ra+1	Ra+2
1D	S32
1D_BUFFER	S32/U32
1D_ARRAY	S32	U16
2D	S32	S32
2D_ARRAY	S32	S32	U16
3D	S32	S32	S32

For 1D_BUFFER, the coordinate is S32 if .clamp is .NEAR. Otherwise, the coordinate is interpreted as U32. The 1D_ARRAY and 2D_ARRAY array indices are treated as U16, meaning only the 16 LSBs of the register value are used.

The .clamp field specifies how to clamp out of bounds addresses (too high or low).

.IGN ignores SUST operations to out-of-bounds addresses.
.NEAR indicates that an out-of-bounds address will clamp to the nearest surface boundary.
.TRAP indicates that an out-of-bounds address causes an execution trap. If coordinates exceed bounds, the memory access is treated like an .IGN

Sc contains a pointer to texture header. The possible options for Sc are:

Rc: stored in 32-bit register. (Rc cannot be RZ)
Constant with Immediate address, #tsPtrIdxU13: { const[15:2], 2'b00 }

Size specifier for byte (.D.BA) and coordinate (.D) addressing.

.sz is one of: .U8, .S8, .U16, .S16, .32, .64, .128. .U8 and .S8 are equivalent for SUST .U16 and .S16 are equivalent for SUST .sz Indicates the amount of memory to store from register(s) Rb, Rb+1, Rb+2, Rb+3 (as needed).

Size specifier for pixel (.P) addressing.

.rgba specifies the format and size of the pixel.
.rgba indicates number of color components to store from register(s) Rb, Rb+1, Rb+2, Rb+3 (as needed).
Following table shows the format of the source data:

Format of Source Data
Target Surface Format Source Format

UNORM, SNORM, FLOAT F32

UINT U32

SINT S32
The input data register is assumed to contain R in the lowest register (i.e., in Rb), followed by G, then B, and then A using successive registers as necessary. If a component is missing in the source format, then missing data will be filled with zeros. Extra components in the source data will be ignored. All data format conversions are performed as specified in the Microsoft DX specs.

*Format of Source Data*
Target Surface Format	Source Format
UNORM, SNORM, FLOAT	F32
UINT	U32
SINT	S32

All surface stores are uncached at L1 level, regardless of .cop. Within the L1 cache, surface operations to the same coordinates as cached Texture operations will not invalidate cached data lines.

If the surface being accessed is disabled, the write will be silently dropped.

When used in a pixel shader by helper pixels or killed pixels, SUST automatically turned into NOP for that thread. This is to prevent unwanted writes to global memory by pixels with zero raster coverage or by pixels that have been using the KIL operation. These the threads will not participate in any SUST operations.

SUST : Surface Store

Format

Description

Examples: