SURED

SPA 5.0:
        {@{!}Pg}   SURED.D{.BA}.dim.op{.sz}{.clamp}   [Ra], Rb, #tsPtrIdxU13   {&req_6}   {&rdN}   {?sched}   ;   
        {@{!}Pg}   SURED.D{.BA}.dim.op{.sz}{.clamp}   [Ra], Rb, Rc             {&req_6}   {&rdN}   {?sched}   ;   

        .dim    {.1D, .1D_BUFFER, .1D_ARRAY, .2D, .2D_ARRAY, .3D}

        .mode   {.D} 
            .D      This mode specifies load from surface as raw data of size .sz, without any format conversion.
                    In this mode, if .BA (ByteAddress) is specified, 
                         the x-coordinate is assumed to be in bytes, aligned on a .sz boundary. 
                         Otherwise, x-ordinate is treated as sample co-ordinate and scaled by .sz in hardware.

        .op     {.ADD, .MIN, .MAX, .INC, .DEC, .AND, .OR, .XOR}
        .sz     {.U32*, .S32, .U64, .S64, .F32.FTZ.RN, .F16x2.FTZ.RN, .SD32, .SD64}
        .BA     x-coordinate is specified as byte-address. (in .D mode)
        .clamp  {.IGN, .NEAR*, .TRAP}

                                  
    Operands
    ------------------------------------
    Ra             Coordinates 
    Rb             Reduction operand.  
    #tsPtrIdxU13   This immediate index (word address) is used to fetch the packed header+sampler pointer entry from constant cache.  The bank from which
                   it is fetched  is determined by bundle state. The constant bank entry is 32 bit structure of the form
                   "samplerPtr[31:20] | headerPtr[19:0]". (Surface instructions ignore sample pointers).
                   Any header pointer greater than one specified in SetTexHeaderPoolC.MaximumIndex  will be regarded as an "invalid" texture.
    Rc             In bindless mode, Rc register is used to pass the "samplerPtr[31:20] | headerPtr[19:0]". 
                   Note: Ra/Rc cannot be RZ register.


    -------------------------------------------------------------------------
                            Reduction Operations
    .op    .sz                                            Description,  M is [Ra]           
    -------------------------------------------------------------------------
    .ADD   .U32 .S32 .SD32 .U64 .F32.FTZ.RN .F16x2.RN      M = M + Rb;
    .MIN   .U32 .S32 .SD32 .U64 .S64 .SD64  .F16x2.RN      M = min(M, Rb);
    .MAX   .U32 .S32 .SD32 .U64 .S64 .SD64  .F16x2.RN      M = max(M, Rb);
    .INC   .U32                                            M = (M >= Rb)? 0 : (M + 1);
    .DEC   .U32                                            M = (M == 0 || M > Rb)? Rb : M - 1;
    .AND   .U32 .S32 .SD32 .U64                            M = M & Rb;
    .OR    .U32 .S32 .SD32 .U64                            M = M | Rb;
    .XOR   .U32 .S32 .SD32 .U64                            M = M ^ Rb;
    -------------------------------------------------------------------------

SURED performs an reduction on pitch or blocklinear surfaces in global memory.

Register Ra specifies surface coordinates. The number of coordinates depends upon surface dimension. Ra must follow register alignment rules for given number of coordinates.

*Surface Coordinate packing in Ra*
.dim	Ra	Ra+1	Ra+2
1D	S32
1D_BUFFER	S32/U32
1D_ARRAY	S32	U16
2D	S32	S32
2D_ARRAY	S32	S32	U16
3D	S32	S32	S32

For 1D_BUFFER, the coordinate is S32 if .clamp is .NEAR. Otherwise, the coordinate is interpreted as U32. The 1D_ARRAY and 2D_ARRAY array indices are treated as U16, meaning only the 16 LSBs of the register value are used.

The .clamp field specifies how to clamp out of bounds addresses (too high or low).

.IGN stores to nearest edge sample (ignores the clamping status).
.NEAR indicates that an out-of-bounds address will clamp to the nearest surface boundary
.TRAP indicates that an out-of-bounds address causes an execution trap. If coordinates exceed bounds, the memory access is treated like an .IGN.

Sc contains a pointer to texture header. The possible options for Sc are:

Rc: stored in 32-bit register. (Rc cannot be RZ)
Constant with Immediate address, #tsPtrIdxU13: { const[15:2], 2'b00 }

Size specifier for byte (.D.BA) and coordinate (.D) addressing.

.sz is one of:
.U32, .S32, .U64, .S64, .F32.FTZ.RN, .F16x2.FTZ.RN,.SD32, and .SD64

.SD32 implies either U32 or S32 (based on surface header)
.SD64 implies either U64 or S64 (based on surface header)

.sz Indicates the amount of memory to store from register(s) Rb, Rb+1 (as needed).

All surface operations are uncached at L1 level, regardless of .cop. Within the L1 cache, surface operations to the same coordinates as cached Texture operations will not invalidate cached data lines.

If the surface being accessed is disabled, the update will be silently dropped.

When used in a pixel shader by helper pixels or killed pixels, SURED automatically turned into NOP for that thread. This is to prevent unwanted writes to global memory by pixels with zero raster coverage or by pixels that have been using the KIL operation. These the threads will not participate in any SURED operations.

SURED : Atomic Reduction on surface memory

Format

Description

Examples: