SPA 5.0:
{@{!}Pg} SHR{.fmt}{.mode}{.xmode}{.BREV} Rd{.CC},Ra,Sb {&req_6} {?sched} ;
.fmt: {.U32,.S32*}
Select between logical (unsigned) and arithmetic (signed) shift right
.mode: {.W, .C*}
.C (Clamp): Sb is treated as an unsigned integer and is clamped to (0-32).
.W (Wrap): Sb is treated as an unsigned integer and is masked by 0x001f
.xmode: { < NULL >*, .X, .XHI }
Extended precision support for shifts. The default is no
extended precision (32-bit shift).
.BREV Bit reverse all the bits in Ra before the shift operation
.CC: Write condition codes
SHR allows the following source Sb:
Sb(register)
Sb(constant with immediate address)
Sb(#IMM20)
Shift Ra right by contents of Sb. The msb insertion is sign_bit for signed Ra source and 0 for unsigned.
An extended-precision right shift is performed by processing words in order from least-significant to most-significant. At the end of the extended-precision shift sequence, the condition code flags reflect the overall multi-word result. The carry flag is set by the initial right shift instruction, and sign and overflow flags are set by the final right shift instruction using .XHI mode. The zero flag value is accumulated by shift instructions in either .X or .XHI mode.
SHR.W R0,R1,R7; SHR R0,R1,0x9;