R2P : Move Register To Predicate/CC Register

Format

SPA 5.0:
        {@{!}Pg}   R2P   PR, Ra{.extract} {, SbMask}   {&req_6}   {?sched>=?WAIT1}   ;   
        {@{!}Pg}   R2P   CC, Ra{.extract} {, SbMask}   {&req_6}   {?sched>=?WAIT1}   ;   

 .extract  : {.B0*,.B1, B2, B3}
             .B0 selects Ra[ 7: 0] for the source of new CC/PR bits  
             .B1 selects Ra[15: 8] for the source of new CC/PR bits
             .B2 selects Ra[23:16] for the source of new CC/PR bits   
             .B3 selects Ra[31:24] for the source of new CC/PR bits

Source operand SbMask may have one of these forms:
    Rb                          32-bit register
    c[ImmU05][ImmU16]           32-bit constant with immediate byte address
    ImmS20                      32-bit sign-extended 20-bit immediate

Description

R2P writes selected bits of Predicate Register PR or Condition Code register CCwith register Ra bits. Bits 7:0 of source operand SbMask select which PR or CC bits are written with Ra bits. Operand SbMask defaults to 0xFF when omitted, thus writing all bits of PR/CC.

Predicate Register PR holds the predicates P0 - P6 for each thread arranged in the 16-bit layout below.

         Predicate Register PR
     7    6    5    4    3    2    1    0 
  +----+----+----+----+----+----+----+----+
  |  0 | P6 | P5 | P4 | P3 | P2 | P1 | P0 |
  +----+----+----+----+----+----+----+----+
Condition code Register CC holds the condition code CC flags ZF, SF, CF, and OF for each thread, arranged in the 16-bit layout below.

        Condition Code Register CC
   7    6    5    4    3    2    1    0 
  +----+----+----+----+----+----+----+----+
  |  0 |  0 |  0 |  0 | OF | CF | SF | ZF |
  +----+----+----+----+----+----+----+----+

The .extract modifier specifies which byte (byte 3/2/1/0) is used to write the CC or PR state. If not specified, byte 0 of source Sa is used.

SbMask bits 7:0 specify which PR or CC bits are written; SbMask bits 31:8 are ignored. A SbMask bit of 1 specifies that corresponding PR/CC bit is written with a bit from register Ra; a SbMask bit of 0 leaves that PR bit unchanged.

Examples:

R2P   PR, R5;               // PR = R5.B0;
R2P   PR, R5.B0, 0xFF;      // PR = R5.B0;
R2P   PR, R5.B0, 0xFF;      // PR = R5.B0;
R2P   PR, R5.B2, 0xFF;      // PR = R5.B2;

R2P   CC, R5.B1, 0x0F;      // CC = R5[11:8];
R2P   CC, R5, (1<<3); // CC.OF = R5[bit 3];

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