P2R : Move Predicate Register To Register

SPA 5.0:
        {@{!}Pg}   P2R{.insert}   Rd, PR                {&req_6}   {?sched>=?WAIT1}   ;   
        {@{!}Pg}   P2R{.insert}   Rd, PR, Ra , SbMask   {&req_6}   {?sched>=?WAIT1}   ;   

        {@{!}Pg}   P2R{.insert}   Rd, CC                {&req_6}   {?sched>=?WAIT1}   ;   
        {@{!}Pg}   P2R{.insert}   Rd, CC, Ra , SbMask   {&req_6}   {?sched>=?WAIT1}   ;   

 .insert  : {.B0*,.B1, B2, B3}
             .B0 merges CC/PR bits in Ra[ 7: 0] based on SbMask and writes the result in Rd.   
             .B1 merges CC/PR bits in Ra[15: 8] based on SbMask and writes the result in Rd. 
             .B2 merges CC/PR bits in Ra[23:16] based on SbMask and writes the result in Rd.    
             .B3 merges CC/PR bits in Ra[31:24] based on SbMask and writes the result in Rd. 

Source operand SbMask may have one of these forms:
    Rb                          32-bit register
    c[ImmU05][ImmU16]           32-bit constant with immediate byte address
    ImmS20                      32-bit sign-extended 20-bit immediate

P2R writes destination register Rd with the merge of bits from Predicate Register PR or Condition Code register CC and bits from register Ra. Bits 7:0 of source operand SbMask select which individual bits of PR/CC bits are read. A SbMask bit of 1 reads the corresponding PR/CC bit; an SbMask bit of 0 reads an Ra bit from the byte specified by .insert modifier in register Ra.

Predicate Register PR holds the predicates P0 - P6 for each thread arranged in the 8-bit layout below.

         Predicate Register PR
     7    6    5    4    3    2    1    0 
  +----+----+----+----+----+----+----+----+
  |  0 | P6 | P5 | P4 | P3 | P2 | P1 | P0 |
  +----+----+----+----+----+----+----+----+

Condition code Register CC holds the condition code CC flags ZF, SF, CF, and OF for each thread, arranged in the 8-bit layout below.

        Condition Code Register CC
   7    6    5    4    3    2    1    0 
  +----+----+----+----+----+----+----+----+
  |  0 |  0 |  0 |  0 | OF | CF | SF | ZF |
  +----+----+----+----+----+----+----+----+

The simple form of P2R is assembled as P2R.B0 Rd, PR/CC, RZ, 0xFF;. Simple P2R writes register Rd with zero-extended PR/CC.

Optional .insert modifier allows merging PR/CC register at arbitrary byte of register Ra.

P2R     R5, PR;                         // R5 = PR;
P2R     R0, PR, RZ, 0xFF;               // R0 = PR;
P2R.B0  R0, PR, R0, 0xFF;               // R0.B0 = PR;
P2R.B1  R0, PR, R0, 0xFF;               // R0.B1 = PR;

P2R.B0  R0, CC, R5, 0x1;                  // R0 = {R5[31:1], CC.ZF;}
P2R     R0, CC, R0, (1<<3);         // R0[3] = CC.OF