MOV : Move

Format:

SPA 5.0:
        {@{!}Pg}   MOV      Rd, Sb {, #PixMaskU04}      {&req_6}   {?sched}   ;   
        {@{!}Pg}   MOV32I   Rd, #Imm32 {, #PixMask04}   {&req_6}   {?sched}   ;   

MOV source operand Sb may have one of these forms:
    Rb                      // 32-bit register
    c[ImmU05][ImmU16]       // 32-bit constant with immediate slot and byte address (or c[ImmU20])
    ImmS20                  // 32-bit sign-extended 20-bit immediate

Description:

Move source operand to destination register Rd, as uninterpreted bits.

The optional 4-bit pixel enable mask ImmU04 defaults to value 0xF (all enabled) when omitted.

Additional Information:

TXD emulation may specify the optional 4-bit mask ImmU04 to enable (1) or disable (0) each of the pixels in a pixel quad. The same mask is applied to all quads in a warp. The correspondence between pixels and mask bit positions (bit 0 is the least-significant right-most bit) is as follows:

    0 1
    2 3

Note: This order may be different from the pixel order of other pixel masks used in the GPU.

Examples:

MOV    R0, c[0][124];
MOV32I R0, 0x3F800000;

Back to Index of Instructions