LDC : Load Constant

SPA 5.0:
        {@{!}Pg}   LDC{.sz}        Rd, c[#ImmU05][#ImmU16]      {&req_6}   {&rdN}   {&wrN}   {?sched}   ;   
        {@{!}Pg}   LDC{.sz}{.ad}   Rd, c[#ImmU05][Ra+#ImmS16]   {&req_6}   {&rdN}   {&wrN}   {?sched}   ;   

 .sz:     { .U8, .S8, .U16, .S16, .32*, .64, .INVALID } 
 .ad:     { .IA*, .IL, .IS, .ISL } 

Move constant (which might be indexed) into destination. This is a bit-wise move. LDC always uses the indexed C$, not the immediate C$, and supports 8-bit to 128-bit loads.

If Ra is not specified or Ra is RZ, the address is an unsigned 16-bit immediate. If Ra is specified and is not RZ, the address is the sum of register Ra and an 16b signed immediate.

Source Ra is unsigned and in bytes, immediate is in bytes.

The constant bank is given by #ImmU05. There are a maximum of 32 constant banks of size 64 KB each. Out of bounds addresses result in 0s being written back.

The address calculation math wraps silently at 32-bits. The hardware supports up to 18 banks (8 in Compute), and will return 0 for unsupported banks.

There are three address behaviours for LDC with an indexed address:

  00: IA                                 // DX10 Mode, Default
      bank = #ImmU05;
      addr = Ra + #ImmS16;

  01: IL                                 // Linear Address Mode
      bank = #ImmU05 + ((Ra + #ImmS16) >> 16);
      addr = (Ra + #ImmS16) & 0xffff;

  10: IS                                 // Segmented Address
      bank = #ImmU05 + (Ra >> 16);
      addr = #ImmS16 + (Ra & 0xffff);

  11: ISL                                // DX11 Mode (Segmented Address with bounds checking)
      bank = #ImmU05 + (Ra >> 16);
      addr = #ImmS16 + (Ra & 0xffff);
      if(bank > 13)                      // 14 banks are allowed for DX indexing, others are reserved
         result = 0;

The suffix .sz specifies the size in bits to load from memory. Sizes require register destination alignment and address alignment.

Misaligned addresses/register will result in an error.

Additional Information:

LDC.32.IA  R2,c[0][R1 + 0x404];

LDC.64     R4,c[7][0x400];
LDC.64     R6,c[7][0x408];