SPA 5.0:.dstfmt: { .F16, .F32*, .F64, INVALID }
{@{!}Pg}
I2F{.dstfmt.srcfmt}{.rnd}
Rd{.CC},{-}{|}Sb{.extract}{|}
{&req_6}
{&rdN}
{&wrN}
{?sched}
;
.srcfmt: { .U8, .S8, .U16, .S16, .U32, .S32*, .U64, .S64 }
----------------------------------------
.SRCFMT .DSTFMT Status
----------------------------------------
.S8 ,.U8 .F16 OK
.S8 ,.U8 .F32 OK
.S8 ,.U8 .F64 Illegal ---------------------------------------- .S16,.U16 .F16 OK .S16,.U16 .F32 OK .S16,.U16 .F64 Illegal ---------------------------------------- .S32,.U32 .F16 Illegal .S32,.U32 .F32 OK .S32,.U32 .F64 OK ---------------------------------------- .S64,.U64 .F16 Illegal
.S64,.U64 .F32 OK
.S64,.U64 .F64 OK
----------------------------------------
.rnd: { .RN*, .RM, .RP, .RZ }
.CC: Write condition codes
.extract: byte/word extraction parameter
if (.srcfmt = U16/S16) {.H0*,.H1}
where
.H0 // Sb[15:00]
.H1 // Sb[31:16]
else { B0*,.B1,.B2,.B3}
where
.B0 // Sb[07:00]
.B1 // Sb[15:08], .srcfmt must be .U8 or .S8
.B2 // Sb[23:16], .srcfmt must be .U8 or .S8
.B3 // Sb[31:24], .srcfmt must be .U8 or .S8
.H0/.H1 only legal if srcfmt=.U16 or .S16
.B0/.B1/.B2/.B3 only legal if srcfmt=.U8 or .S8
The following source combinations are allowed for all non-64-bit formats:
Sb(register)
Sb(constant with immediate address)
Sb(sign-extended #IMM20)
The following source combinations are allowed for 64-bit formats:
Sb(register - must be even aligned)
Sb(64-bit constant with immediate address --
Upper 32-bits are taken from constant, lower 3 address bits must be 0x4,
Lower 32 bits of Sb are always 0)
Sb(sign-extended #IMM20<<32)
The integer contents of source are moved into destination with optional extraction/conversions.
Here are the steps in the process:
Sb.H0 // Sb[15:00], .srcfmt must be .U16 or .S16
Sb.H1 // Sb[31:16], .srcfmt must be .U16 or .S16
Sb.B0 // Sb[07:00], .srcfmt must be .U8 or .S8
Sb.B1 // Sb[15:08], .srcfmt must be .U8 or .S8
Sb.B2 // Sb[23:16], .srcfmt must be .U8 or .S8
Sb.B3 // Sb[31:24], .srcfmt must be .U8 or .S8
.U8 : input 8b, 0 extend
.S8 : input 8b, sign extend
.U16 : input 16b, 0 extend
.S16 : input 16b, sign extend
.U32 : input 32b, 0 extend // cannot convert to fp16
.S32 : input 32b, sign extend // cannot convert to fp16
.U64 : input 64b, 0 extend // cannot convert to fp16
.S64 : input 64b, sign extend // cannot convert to fp16
0: .RN - Mantissa lsb round to nearest even
1: .RM - Mantissa lsb round towards -Infinity
2: .RP - Mantissa lsb rount towards +Infinity
3: .RZ - Mantissa lsb round towards 0
I2F R0,R1;