FMUL : FP32 Multiply

Format:

SPA 5.0:
        {@{!}Pg}   FMUL{.fmz}{.scale}{.rnd}{.SAT}   Rd{.CC},{-}Ra,{-}Sb   {&req_6}   {?sched}   ;   
        {@{!}Pg}   FMUL32I{.fmz}{.SAT}              Rd{.CC},Ra,#Imm32     {&req_6}   {?sched}   ;   

 .fmz:       { < NULL >*, .FTZ, .FMZ, INVALID } 
             .fmz controls denorm flush and multiply mode.
               < NULL >: Denorms supported. No special handling of 0.
                         This is default.
               .FTZ:     Flush input/output denorms to sign-preserving zero.
               .FMZ:     Flush input/output denorms to sign-preserving zero AND
                         if either source is 0.0, the product is forced to +0.0
                         (even if other source is infinity or NaN), regardless
                         of the input signs. The 0.0 test is done after input
                         denorm flush.

 .scale:     { .D8, .D4, .D2, < NULL >*, .M2, .M4, .M8, INVALID } 
             Scaling Mode (.scale):
               Multiply Ra by 2^n (-3<=n<=3) before the product:
                 .D8                       // divide by 8.0
                 .D4                       // divide by 4.0
                 .D2                       // divide by 2.0
                 < NULL >                  // pass-through. This is default.
                 .M2                       // multiply by 2.0
                 .M4                       // multiply by 4.0
                 .M8                       // multiply by 8.0

 .rnd:       { .RN*, .RM, .RP, .RZ } 
             .RN - Round to the nearest even.
             .RM - Round towards -Infinity
             .RP - Round towards +Infinity
             .RZ - Round towards 0

 .SAT:       output saturate (.SAT) to (+0.0f,1.0f), with NaN converted to +0.0f.

 .CC:        Write condition codes

FMUL allows the following source Sb:
    Sb(register)
    Sb(constant with immediate address)
    Sb(#IMM20<<12)

FMUL32I always use .RN rounding mode.

Description:

Multiply fp32 sources into destination register. Optionally scale the input Ra by .scale. This scaling occurs with unrestricted range, so infinities, denormals and zeros are not newly generated in the intermediate results.

IEEE Rounding Modes

Fp32 operations support all 4 required IEEE-754 2008 rounding modes:

.RN
roundTiesToEven
.RM
roundTowardNegative
.RP
roundTowardPositive
.RZ
roundTowardZero

The optional IEEE rounding mode roundTiesToAway is not supported.

See the IEEE-754 2008 specification, Section 4.3.3.

NaN Behavior:

The chosen NaN behavior for fp32 operations is different than that of fp64 operations. The chosen fp32 behavior is different from Intel's x87/SSE behavior, but is still IEEE-754 2008 compliant when .FMZ is not used: The standard allows canonicalization of the NaN result to be implementation-defined. See the IEEE-754 2008 specification, Section 6.2.

Examples:

FMUL.M2      R0,R1,R2;
FMUL32I.SAT  R0,R1,0x3f900000;

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