FADD : FP32 Add

Format:

SPA 5.0:
        {@{!}Pg}   FADD{.FTZ}{.rnd}{.SAT}   Rd{.CC},{-}{|}Ra{|},{-}{|}Sb{|}   {&req_6}   {?sched}   ;   
        {@{!}Pg}   FADD32I{.FTZ}            Rd{.CC},{-}{|}Ra{|},#Imm32        {&req_6}   {?sched}   ;   

 .FTZ:       Denorm inputs/output is flushed to sign preserving 0.0.

 .rnd:       { .RN*, .RM, .RP, .RZ } 
             .RN - Round to the nearest even.
             .RM - Round towards -Infinity
             .RP - Round towards +Infinity
             .RZ - Round towards 0

 .SAT:       output saturate (.SAT) to (+0.0f,1.0f), with NaN converted to +0.0f.

 .CC:        Write condition codes

FADD allows the following source Sb:
    Sb(register)
    Sb(constant with immediate address)
    Sb(#IMM20<<12)

For FADD32I .rnd defaults to .RN

Description:

Add fp32 sources into destination register.

IEEE Rounding Modes

Fp32 operations support all 4 required IEEE-754 2008 rounding modes:

.RN
roundTiesToEven
.RM
roundTowardNegative
.RP
roundTowardPositive
.RZ
roundTowardZero

The optional IEEE rounding mode roundTiesToAway is not supported.

See the IEEE-754 2008 specification, Section 4.3.3.

NaN Behavior:

The chosen NaN behavior for fp32 operations is different than that of fp64 operations. The chosen fp32 behavior is different from Intel's x87/SSE behavior, but is still IEEE-754 2008 compliant: The standard allows canonicalization of the NaN result to be implementation-defined. See the IEEE-754 2008 specification, Section 6.2.

Examples:

FADD         R0, R1,R2;
FADD32I.FTZ  R0,-R1,0x3f900000;

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