SPA 5.0:
{@{!}Pg} F2I{.FTZ}{.dstfmt.srcfmt}{.rnd} Rd{.CC},{-}{|}Sb{.extract}{|} {&req_6} {&rdN} {&wrN} {?sched} ;
.FTZ: fp32 denorm input is flushed to sign-preserving 0.0.
.dstfmt: { .U16, .S16, .U32, .S32*, .U64, .S64 }
.srcfmt: { .F16, .F32*, .F64}
----------------------------------------
.SRCFMT .DSTFMT Status
----------------------------------------
.F16 .U16 OK
.F16 .S16 OK
.F16 .U32 OK
.F16 .S32 OK
.F16 .U64 Illegal
.F16 .S64 Illegal
----------------------------------------
.F32 .U16 OK
.F32 .S16 OK
.F32 .U32 OK
.F32 .S32 OK
.F32 .U64 OK
.F32 .S64 OK
----------------------------------------
.F64 .U16 Illegal
.F64 .S16 Illegal
.F64 .U32 OK
.F64 .S32 OK
.F64 .U64 OK
.F64 .S64 OK
----------------------------------------
.rnd: { .ROUND*, .FLOOR, .CEIL, .TRUNC }
.CC: Write condition codes
.extract: {.H0,.H1}
.F16 extraction from bottom(H0) or top(H1) 16b.
Only legal if srcfmt==.F16
The following source Sb combinations are allowed for FP16 input:
Sb(register)
Sb(constant with immediate address)
Sb(((#Imm20 & 0x0000_ffff)<<16) | (#Imm20 & 0x0000_ffff))
The following source Sb combinations are allowed for FP32 input:
Sb(register)
Sb(constant with immediate address)
Sb(#IMM20<<12)
The following source Sb combinations are allowed for FP64 input:
Sb(even aligned register)
Sb(64-bit constant with immediate address --
Upper 32-bits are taken from constant, lower 3 address bits must be 0x4,
Lower 32 bits of Sb are always 0)
Sb(#IMM20<<44)
The contents of source are moved into destination with optional conversions.
If the source is .F16 or .F64 or if the destination is .U64 or .S64, .FTZ is ignored.
If destination is .S64 or .U64 format, Rd must be a properly aligned register.
.F16 is 1.5.10 format // denorms are supported/don't-care in all APIs .F32 is 1.8.23 format // denorms NOT supported in DirectX .F64 is 1.11.52 format // denorms are supported/don't-care in all APIs
The following steps are done:
0: .ROUND - Integer Round to nearest even // round
1: .FLOOR - Integer Round towards -Infinity // floor
2: .CEIL - Integer Round towards +Infinity // ceiling
3: .TRUNC - Integer Round towards 0 // truncate
1: to u16 output // clamp(0x0000_0000, 0x0000_FFFF)
2: to s16 output // clamp(0xFFFF_8000, 0x0000_7FFF)
3: to u32 output // clamp(0x0000_0000, 0xFFFF_FFFF)
4: to s32 output // clamp(0x8000_0000, 0x7FFF_FFFF)
5: to u64 output // clamp(0x0000_0000_0000_0000, 0xFFFF_FFFF_FFFF_FFFF)
6: to s64 output // clamp(0x8000_0000_0000_0000, 0x7FFF_FFFF_FFFF_FFFF)
If the source is NaN, following rule is applied.
If(srcfmt != F64 and dstfmt != U64 and dstfmt != S64 ) {
Rd = 0;
} else { // srcfmt==F64 or dstfmt==U64 or dstfmt==S64
if(dstfmt == U32 or S32) {
Rd = 32h8000_0000;
} else { // dstfmt == U64 or S64
Rd = 64h8000_0000_0000_0000;
}
}
F2I.U32.F32.ROUND R0,R1;