SPA 5.0:
{@{!}Pg}
DSET{.bval}.cmp
Rd{.CC}, {-}{|}Ra{|}, {-}{|}Sb{|}
{&req_6}
{&rdN}
{&wrN}
{?sched}
;
.bval: { .BM*, .BF } Boolean mask or Boolean float value to set in Rd, default .BM .cmp: { .F, .LT, .EQ, .LE, .GT, .NE, .GE, .NUM, FP64 numeric comparisons .NAN, .LTU, .EQU, .LEU, .GTU, .NEU, .GEU, .T } FP64 numeric or Unordered comparisons .bop: { .AND, .OR, .XOR } Boolean op with predicate {!}Pp .CC: Write condition codes The following source Sb is allowed: Sb(even aligned register) Sb(64-bit constant with immediate address) if lower 3 address bits are 0x4, the 64 bit constant is (c[][addr&~7|0x4] << 32) if lower 3 address bits are 0x0, the 64 bit constant is (c[][addr|0x4] << 32) | c[][addr]) Sb(#IMM20<<44)
{@{!}Pg}
DSET{.bval}.cmp.bop
Rd{.CC}, {-}{|}Ra{|}, {-}{|}Sb{|}, {!}Pp
{&req_6}
{&rdN}
{&wrN}
{?sched}
;
Note that the source registers have to be even aligned.
DSET{.bval}.cmp.bop compares FP64 register pair Ra and source operand Sb with FP64 comparison operation .cmp, combines the Boolean comparison result with predicate operand {!}Pp using the Boolean operation .bop, and sets 32-bit destination register Rd to integer ~0x0 or single-precision fp32 floating point 1.0f if the comparison is true, otherwise it sets Rd to 0. The Boolean operation .bop may be .AND, .OR, or .XOR, corresponding to the C Boolean operations &, |, and ^.
if (.BM) Rd = ( (Ra .cmp Sb) .bop {!}Pp )? 0xFFFF_FFFF: 0; // SET Boolean mask all 1s or all 0s if (.BF) Rd = ( (Ra .cmp Sb) .bop {!}Pp )? 0x3F80_0000: 0; // SET FP32 Boolean 1.0f or 0.0f
Use .bop {!}Pp for nested conditions, with an inner comparison of Ra vs. Sb, conditioned on an outer predicate Pp.
The simple instruction format without .bop {!}Pp assembles as .AND PT, with the following effective functionality:
if (.BM) Rd = (Ra .cmp Sb)? 0xFFFF_FFFF: 0; // Set Boolean mask all 1s or all 0s if (.BF) Rd = (Ra .cmp Sb)? 0x3F80_0000: 0; // Set Boolean float FP32 1.0f or 0.0f
Double precision compares do NOT flush denormalized operands to zero prior to comparison.
DSET.NEU.AND R1, R2, -|R4|, P3;