SPA 5.0:
{@{!}Pg} DMUL{.rnd} Rd{.CC},{-}Ra,{-}Sb {&req_6} {&rdN} {&wrN} {?sched} ;
.rnd: { .RN*, .RM, .RP, .RZ }
.RN - Round to the nearest even.
.RM - Round towards -Infinity
.RP - Round towards +Infinity
.RZ - Round towards 0
.CC: Write condition codes
The following source Sb is allowed:
Sb(even aligned register)
Sb(64-bit constant with immediate address)
if lower 3 address bits are 0x4, the 64 bit constant is (c[][addr&~7|0x4] << 32)
if lower 3 address bits are 0x0, the 64 bit constant is (c[][addr|0x4] << 32) | c[][addr])
Sb(#IMM20<<44)
Note that the registers have to be even aligned.
Multiply fp64 sources into destination register.
Fp64 operations support all 4 required IEEE-754 2008 rounding modes:
The optional IEEE rounding mode roundTiesToAway is not supported.
See the IEEE-754 2008 specification, Section 4.3.3.
The chosen NaN behavior for fp64 operations is different than that of fp32 operations. The chosen fp64 behavior matches Intel's SSE behavior, and is IEEE-754 2008 compliant. See the IEEE-754 2008 specification, Section 6.2.
DMUL R0,R2,R6;