SPA 5.0:
{@{!}Pg} DMNMX Rd{.CC},{-}{|}Ra{|},{-}{|}Sb{|},{!}SPa {&req_6} {&rdN} {&wrN} {?sched} ;
.CC: Write condition codes
The following source Sb is allowed:
Sb(even aligned register)
Sb(64-bit constant with immediate address)
if lower 3 address bits are 0x4, the 64 bit constant is (c[][addr&~7|0x4] << 32)
if lower 3 address bits are 0x0, the 64 bit constant is (c[][addr|0x4] << 32) | c[][addr])
Sb(#IMM20<<44)
Note that the registers have to be even aligned.
Minimum or maximum of fp64 sources into destination.
The minimum operation is chosen if the source predicate is TRUE. Otherwise, the maximum operation is used.
If the values being compared are both 0.0 then +0.0 > -0.0.
The chosen NaN behavior for fp64 operations is different than that of fp32 operations. The chosen fp64 behavior matches Intel's SSE behavior, and is IEEE-754 2008 compliant. See the IEEE-754 2008 specification, Sections 6.2, and 5.3.1.
DMNMX R0,R2,R6,PT; // MIN DMNMX R0,R2,R6,!PT; // MAX