SPA 5.0:
{@{!}Pg} DFMA{.rnd} Rd{.CC},{-}Ra,{-}Sb,{-}Sc {&req_6} {&rdN} {&wrN} {?sched} ;
.rnd: { .RN*, .RM, .RP, .RZ }
.RN - Round to the nearest even.
.RM - Round towards -Infinity
.RP - Round towards +Infinity
.RZ - Round towards 0
.CC: Write condition codes
The following sources Sb, Sc are allowed:
Sb(register), Sc(register)
Sb(constant with immediate address), Sc(register)
Sb(register), Sc(constant with immediate address)
Sb(#IMM20<<44), Sc(register)
The constant operand has two modes:
if lower 3 address bits are 0x4, the 64 bit constant is (c[][addr&~7|0x4] << 32)
if lower 3 address bits are 0x0, the 64 bit constant is (c[][addr|0x4] << 32) | c[][addr])
Note that the registers have to be even aligned.
The product of Ra and Sb is computed to infinite precision and then Sc is added with a precision sufficient to guarantee that after rounding, the result is identical to that of an add with infinite precision followed by the rounding. The rounding is done to double precision (fp64) using the .rnd rounding mode.
See the IEEE-754 2008 standard, section 5.4.1 for details.
Fp64 operations support all 4 required IEEE-754 2008 rounding modes:
The optional IEEE rounding mode roundTiesToAway is not supported.
See the IEEE-754 2008 specification, Section 4.3.3.
The chosen NaN behavior for fp64 operations is different than that of fp32 operations. The chosen DFMA behavior is in the spirit of Intel's SSE behavior, and is IEEE-754 2008 compliant. See the IEEE-754 2008 specification, Section 6.2.
DFMA R0,R2,R4,R6;