SPA 5.0:
Immediate attribute loads:
{@{!}Pg} ALD{.io}{.P}{.sz} Rd,a[#ImmU10]{,Rb} {&req_6} {&rdN} {&wrN} {?sched} ;
Indexed patch attribute loads:
{@{!}Pg} ALD{.io}.P{.sz} Rd,a[Ra + #ImmS11]{,Rb} {&req_6} {&rdN} {&wrN} {?sched} ;
Indexed VTG (Vertex,Tess,Geom) attribute loads:
{@{!}Pg} ALD{.io}.PHYS{.sz} Rd,a[Ra]{,Rb} {&req_6} {&rdN} {&wrN} {?sched} ;
.io: {.I*,.O}
Load from the input ISBE (.I) or output ISBE (.O). Only VSa, VSb, TI, and TS can use .O option.
.P: Load patch attributes
.sz: { .32*, .64, .96, .128 }
.PHYS: Indexed mode for VTG attribute load that uses physical attribute number determined via AL2P
.PHYS is encoded as .P=0 and Ra!=RZ and imm=0
vector ALD/AST disallowed when .PHYS modifier is used.
Load VTG (Vertex,Tess,Geom) attribute(s).
If Ra is not specified or Ra is RZ, the input address is an unsigned 10b immediate. The immediate is in bytes.
If Ra is specified and is not RZ, the immediate has to be zero and value in Ra register is the al2pResult_vtg_t data structure result of AL2P instruction.
Vertex shaders do not need to specify the vertex handle Rb , and will raise an ILLEGAL_INSTR_ENCODING error when Rb != RZ. Geometry and Tessellation shaders must specify Rb, since it allows access to the vertex neighbourhood.
The .P modifier is designed to allow for reading of Per-Patch attributes by Tessellation Shaders (TS). Unlike normal vertex attributes, patch attributes are stored per patch (as opposed to per-vertex), so an Rb vertex index is ignored. Patch attributes also exist in a different address space which is not controlled by an IMAP/OMAP (so there is no defaulting). As part of the shader program header, a Tessellation Shader will declare the size of its patch attribute buffer (8,16,32,64,128). This means that TI/TS shaders must agree on the size and format of the Patch Attribute section, since there is no HW enforced pipe to line up inputs/outputs.
Generic patch attributes are not specifiable without a TI shader. However, a TS shader can still read the TESSELLATION_LOD_* attributes even if a TI shader is not being used.
When accessing per-primitive attributes (PRIMITIVE_ID), the vertex specified by Rb is ignored and the implicit primitive handle is used instead.
An input BMAP (buffer map) is formed from the IMAP (input map) of the current shader, the OMAP (output map) of the previous shader, and the address of the attribute. An output BMAP is formed from the IMAP of the next shader, the OMAP of the current shader, and the address of the attribute.
The ALD.I or ALD.O return value depends on the BMAP, and will receive a return value that is one of:
For the most common usage cases, the BMAP Definition is simply:
input BMAP = (IMAP from current stage & OMAP of previous stage) output BMAP = (OMAP from current stage & (IMAP from next stage | ST_REQ from current stage))
If .I option: // load from input ISBE
For an attribute address, the following table describes the behavior:
----------------------------------------------------------------------------------------------
Previous Stage
input BMAP write status ALD Return Value
----------------------------------------------------------------------------------------------
0 * Default
1 0 Garbage (ISBE leftover) or HW-generated Attribute Value
1 1 Output From Previous Stage
----------------------------------------------------------------------------------------------
If .O option: // load from output ISBE, not possible for GS
For an attribute address, the following table describes the behavior:
----------------------------------------------------------------------------------------------
Current Stage
output BMAP write status ALD Return Value
----------------------------------------------------------------------------------------------
0 * Default
1 0 Garbage (ISBE leftover)
1 1 Output From Current Stage
----------------------------------------------------------------------------------------------
Defaulted ALD will return 0x0 or 0x3f80_0000, depending on the address. Reading attribute addresses above 1024 (256*4) or below 0 will return 0x0.
When doing a vector load, ALD will access up to 4 consecutive logical attribute addresses. If a particular logical attribute address is not enabled, then the default value is returned for that logical attribute.
Alignment applies to both register and attribute index. LSB bits are dropped for alignment:
.32 forces (RA+#ImmS11) 2 lsb to 00. .64 forces Rd register address[0:0] to 0 and (Ra+#ImmS11) 3 lsb to 000. .96/.128 forces Rd register address[1:0] to 00 and (Ra+#ImmS11) 4 lsb to 0000.
Handling of corrupted Rb (vertex index) for Geometry/Tessellation shader:
1. Sass bug if Rb missing in assembler syntax for Geom/Tess.
2. In range 0-ISBE vtx size (swiss cheese):
(a) valid for thread, result is valid
(b) invalid for source thread (a vertex from a different primitive), cannot detect,
treat as (a)
3. Out of range 0-ISBE vtx size: return 0 and optional Trap
ALD R0,a[16]; // no vertex handle for VS ALD R0,a[R1],R5; // use vertex handle for GS ALD.P R0,a[R1+4],R5; // patch attrib load using AL2P to do indexed ALD: AL2P.I.64 R0, R1, 12; ALD.I.PHYS.64 R2, a[R0] ;